Glossary:
DecCIC - Decimation rate across the CIC filter
DecHB1- Decimation rate across the small Half Band FIR (HB1)
DecHB2 - Decimation rate across the large Half Band FIR (HB2)

For the N210 Rx path (Tx will be similar) ADC -> Packetization, sum the following:

Input register: 1
DC Offset Correction: 1
IQ Balance: 2
IQ Swap: 1
CORDIC: 21
Clip: 1
CIC Filter: 5+6*DecCIC
HB1: 7+6*DecCIC
HB2: 9+8*(DecCIC*DecHB1*2)
Clipping and Gain: 3

This is the number of 100MHz (10nS) clock cycles used in the DSP pipeline before packets are timestamped and packetized.

For example if you had configured N210 to produce a 1MHz sample stream, thats Decimation=100 which maps to : 
DecCIC=25, DecHB1=2, DecHB2=2. This makes group delay ~11.51uS
100: 30 + (5 + 6*25) + (7 + 6*25) + (9 + 8*25*2*2) = 1151

Another example. If you configured N210 to produce a 25<Hz sample stream, thats Decimation = 4 which maps to:
DecCIC=1, DecHB1=2, DecHB2=2. This makes group delay ~950nS.
30 + (5 + 6*1) + (7 + 6*1) + (9 + 8*1*2*2) = 95